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<div class="header">
  <div class="summary">
<a href="#groups">Content</a> &#124;
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">Interrupts and Exceptions</div></div>
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<p>Generic functions to access the Interrupt Controller.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
Content</h2></td></tr>
<tr class="memitem:group__irq__mode__defs"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html">IRQ Mode Bit-Masks</a></td></tr>
<tr class="memdesc:group__irq__mode__defs"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure interrupt line mode. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__irq__priority__defs"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__priority__defs.html">IRQ Priority Bit-Masks</a></td></tr>
<tr class="memdesc:group__irq__priority__defs"><td class="mdescLeft">&#160;</td><td class="mdescRight">Definitions used by interrupt priority functions. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a> = 0
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b">SGI1_IRQn</a> = 1
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07">SGI2_IRQn</a> = 2
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a310ac1f78af36e0e3b9f6b4f15bd9b68">SGI3_IRQn</a> = 3
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac5c03a99c620ff116bafa4cf03dd9a07">SGI4_IRQn</a> = 4
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8adb8d49885011a278ed3c671904da7e6e">SGI5_IRQn</a> = 5
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f9b1989d051c60ad69147e644853a44">SGI6_IRQn</a> = 6
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa1bcd760176e11cdece4386818022631">SGI7_IRQn</a> = 7
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aabbb7ca9433c474bfeade468e8c66455">SGI8_IRQn</a> = 8
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8afa5f21d9fd3df5817a0f871b72bde681">SGI9_IRQn</a> = 9
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a12993bed484c7a70e6281b102d0e27e9">SGI10_IRQn</a> = 10
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a7826ded51cd379774bb076819ff93cdb">SGI11_IRQn</a> = 11
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3425bbf0a6da4d0398e63b48a1345d37">SGI12_IRQn</a> = 12
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace710506c7be1b3b7f9d4a1db2f75391">SGI13_IRQn</a> = 13
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae57c57a817378102db7bc66351c912f1">SGI14_IRQn</a> = 14
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321">SGI15_IRQn</a> = 15
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1d0271c3b3a369c16a9c05ab4ea72ca5">VirtualMaintenanceInterrupt_IRQn</a> = 25
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8acc86d3c23264d2038fd8de56b65059f6">HypervisorTimer_IRQn</a> = 26
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2dde3bb4fc49f71c15bba2c4f0cda2cd">VirtualTimer_IRQn</a> = 27
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac286832ada11ea1575a98149404d8aa7">Legacy_nFIQ_IRQn</a> = 28
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a82e7e80a1d7d70bbe65b380bcda3f309">SecurePhyTimer_IRQn</a> = 29
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aff0bcb9be41e2ba389f9bf1d5f403145">NonSecurePhyTimer_IRQn</a> = 30
, <br />
&#160;&#160;<a class="el" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1718b510599bbe8ebe34aee5c5aa3214">Legacy_nIRQ_IRQn</a> = 31
<br />
 }</td></tr>
<tr class="memdesc:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Definition of IRQn numbers.  <a href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">More...</a><br /></td></tr>
<tr class="separator:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga03ea5d5d67a89acff8a5b02286795a99"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a> (void)</td></tr>
<tr class="memdesc:ga03ea5d5d67a89acff8a5b02286795a99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize interrupt controller.  <br /></td></tr>
<tr class="separator:ga03ea5d5d67a89acff8a5b02286795a99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, <a class="el" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a> handler)</td></tr>
<tr class="memdesc:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register interrupt handler.  <br /></td></tr>
<tr class="separator:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5">IRQ_GetHandler</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the registered interrupt handler.  <br /></td></tr>
<tr class="separator:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable interrupt.  <br /></td></tr>
<tr class="separator:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga544cf4ae0159cc17e259d55898528248"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga544cf4ae0159cc17e259d55898528248"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable interrupt.  <br /></td></tr>
<tr class="separator:ga544cf4ae0159cc17e259d55898528248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8913613a9075a35410af0eb7b275d9e2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2">IRQ_GetEnableState</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga8913613a9075a35410af0eb7b275d9e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get interrupt enable state.  <br /></td></tr>
<tr class="separator:ga8913613a9075a35410af0eb7b275d9e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab35da69354d2e515931580a1308a3a85"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t mode)</td></tr>
<tr class="memdesc:gab35da69354d2e515931580a1308a3a85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure interrupt request mode.  <br /></td></tr>
<tr class="separator:gab35da69354d2e515931580a1308a3a85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadba142ee49ae8f52f76b603c926ad711"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gadba142ee49ae8f52f76b603c926ad711"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get interrupt mode configuration.  <br /></td></tr>
<tr class="separator:gadba142ee49ae8f52f76b603c926ad711"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> (void)</td></tr>
<tr class="memdesc:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get ID number of current interrupt request (IRQ).  <br /></td></tr>
<tr class="separator:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> (void)</td></tr>
<tr class="memdesc:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get ID number of current fast interrupt request (FIQ).  <br /></td></tr>
<tr class="separator:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55638c35efdc7a197b51165929ef0c10"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10">IRQ_EndOfInterrupt</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga55638c35efdc7a197b51165929ef0c10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal end of interrupt processing.  <br /></td></tr>
<tr class="separator:ga55638c35efdc7a197b51165929ef0c10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt pending flag.  <br /></td></tr>
<tr class="separator:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa399f9169f136b3930f0d50247aa22fc"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc">IRQ_GetPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaa399f9169f136b3930f0d50247aa22fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get interrupt pending flag.  <br /></td></tr>
<tr class="separator:gaa399f9169f136b3930f0d50247aa22fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear interrupt pending flag.  <br /></td></tr>
<tr class="separator:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t priority)</td></tr>
<tr class="memdesc:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt priority value.  <br /></td></tr>
<tr class="separator:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3">IRQ_GetPriority</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get interrupt priority.  <br /></td></tr>
<tr class="separator:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337">IRQ_SetPriorityMask</a> (uint32_t priority)</td></tr>
<tr class="memdesc:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set priority masking threshold.  <br /></td></tr>
<tr class="separator:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869">IRQ_GetPriorityMask</a> (void)</td></tr>
<tr class="memdesc:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get priority masking threshold.  <br /></td></tr>
<tr class="separator:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabaa4074988ea9e30523f7ed5a86953c2"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2">IRQ_SetPriorityGroupBits</a> (uint32_t bits)</td></tr>
<tr class="memdesc:gabaa4074988ea9e30523f7ed5a86953c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set priority grouping field split point.  <br /></td></tr>
<tr class="separator:gabaa4074988ea9e30523f7ed5a86953c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga061da812739bdba1e32765ed6501b83c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> (void)</td></tr>
<tr class="memdesc:ga061da812739bdba1e32765ed6501b83c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get priority grouping field split point.  <br /></td></tr>
<tr class="separator:ga061da812739bdba1e32765ed6501b83c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Generic functions to access the Interrupt Controller. </p>
<p>This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.</p>
<dl class="section note"><dt>Note</dt><dd>The default implementation for <a class="el" href="group__GIC__functions.html">Arm GIC (Generic Interrupt Controller)</a> can be found in <a class="el" href="irq__ctrl__gic_8c.html">irq_ctrl_gic.c</a>. It uses <code>weak</code> functions thus it can easily be overwritten by an alternative user implementation if needed.</dd></dl>
<p>The Armv7-A architecture defines a common set of first level exceptions, see table below.</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadNone">Exception   </th><th class="markdownTableHeadNone">CMSIS Handler   </th><th class="markdownTableHeadNone">Offset   </th><th class="markdownTableHeadNone">Description    </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyNone">Reset   </td><td class="markdownTableBodyNone">Reset_Handler   </td><td class="markdownTableBodyNone">0x0000   </td><td class="markdownTableBodyNone">First instruction executed after reset.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyNone">Undefined Instruction (Undef)   </td><td class="markdownTableBodyNone">Undef_Handler   </td><td class="markdownTableBodyNone">0x0004   </td><td class="markdownTableBodyNone">Signals usage of an illegal instructions.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyNone">Supervisor Call (SVC)   </td><td class="markdownTableBodyNone">SVC_Handler   </td><td class="markdownTableBodyNone">0x0008   </td><td class="markdownTableBodyNone">Issued by software using SVC instruction.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyNone">Prefetch Abort (PAbt)   </td><td class="markdownTableBodyNone">PAbt_Handler   </td><td class="markdownTableBodyNone">0x000C   </td><td class="markdownTableBodyNone">Signals a memory abort on istruction fetch.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyNone">Data Abort (DAbt)   </td><td class="markdownTableBodyNone">DAbt_Handler   </td><td class="markdownTableBodyNone">0x0010   </td><td class="markdownTableBodyNone">Signals a memory abort on data read or write.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyNone">Hyp Trap   </td><td class="markdownTableBodyNone">(NOP)   </td><td class="markdownTableBodyNone">0x0014   </td><td class="markdownTableBodyNone">Hypervisor instruction trap, only available with Virtualization Extensions.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyNone">IRQ interrupt   </td><td class="markdownTableBodyNone">IRQ_Handler   </td><td class="markdownTableBodyNone">0x0018   </td><td class="markdownTableBodyNone">Interrupt Request (typically from Interrupt Controller)    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyNone">FIQ interrupt   </td><td class="markdownTableBodyNone">FIQ_Handler   </td><td class="markdownTableBodyNone">0x001C   </td><td class="markdownTableBodyNone">Fast Interrupt Request (typically from Interrupt Controller)   </td></tr>
</table>
<p>By default those handlers are defined as weak empty functions by the <a class="el" href="startup_c_pg.html#startup_c_sec">device specific startup code</a>. Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using <a href="https://arm-software.github.io/CMSIS-RTX">CMSIS-RTX</a>.</p>
<p>The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined in <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> in <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a>. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> SGI0_Handler() {</div>
<div class="line">  <span class="comment">/* </span></div>
<div class="line"><span class="comment">   * Handle Interrupt </span></div>
<div class="line"><span class="comment">   */</span></div>
<div class="line">  </div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> main() {</div>
<div class="line">  <span class="comment">/* Initialize the Interrupt Controller */</span></div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a>();</div>
<div class="line">  </div>
<div class="line">  <span class="comment">/* Register the user defined handler function */</span></div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, SGI0_Handler);  </div>
<div class="line">  </div>
<div class="line">  <span class="comment">/* Set the priority considering the priority grouping */</span></div>
<div class="line">  <span class="keyword">const</span> uint32_t subprio = <a class="code hl_function" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a>();</div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, 1u &lt;&lt; subprio);</div>
<div class="line">  </div>
<div class="line">  <span class="comment">/* Set interrupt mode to falling edge */</span></div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, <a class="code hl_define" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a> | <a class="code hl_define" href="group__irq__mode__defs.html#gacb276aa0488a9bf1aa56e1072d2a15a5">IRQ_MODE_CPU_0</a> | <a class="code hl_define" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a> | <a class="code hl_define" href="group__irq__mode__defs.html#ga99e0f3f6945991d50e766b19e71e0222">IRQ_MODE_TRIG_EDGE_FALLING</a>);</div>
<div class="line">  </div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">  </div>
<div class="line">  <span class="comment">/* Trigger interrupt */</span></div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">  </div>
<div class="line">  <a class="code hl_function" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a>((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_enumvalue" href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga03ea5d5d67a89acff8a5b02286795a99"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a></div><div class="ttdeci">int32_t IRQ_Initialize(void)</div><div class="ttdoc">Initialize interrupt controller.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga061da812739bdba1e32765ed6501b83c"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a></div><div class="ttdeci">uint32_t IRQ_GetPriorityGroupBits(void)</div><div class="ttdoc">Get priority grouping field split point.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga4ad780a3dc23a1b6222de8adcd7c20a7"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a></div><div class="ttdeci">int32_t IRQ_Enable(IRQn_ID_t irqn)</div><div class="ttdoc">Enable interrupt.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga544cf4ae0159cc17e259d55898528248"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a></div><div class="ttdeci">int32_t IRQ_Disable(IRQn_ID_t irqn)</div><div class="ttdoc">Disable interrupt.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga88aedf1dee1061783e6c05c535e7b6c4"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a></div><div class="ttdeci">int32_t IRQ_SetPending(IRQn_ID_t irqn)</div><div class="ttdoc">Set interrupt pending flag.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gaa90aed20ac94420fff4bbbf55c12d4c2"><div class="ttname"><a href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a></div><div class="ttdeci">int32_t IRQ_SetPriority(IRQn_ID_t irqn, uint32_t priority)</div><div class="ttdoc">Set interrupt priority value.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gaad6b03f73b3d3ea2ccbb122484e8bd36"><div class="ttname"><a href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a></div><div class="ttdeci">int32_t IRQ_ClearPending(IRQn_ID_t irqn)</div><div class="ttdoc">Clear interrupt pending flag.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gab35da69354d2e515931580a1308a3a85"><div class="ttname"><a href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a></div><div class="ttdeci">int32_t IRQ_SetMode(IRQn_ID_t irqn, uint32_t mode)</div><div class="ttdoc">Configure interrupt request mode.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gac1fcc16fb8e488d315cfa496f1d71db3"><div class="ttname"><a href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a></div><div class="ttdeci">int32_t IRQ_SetHandler(IRQn_ID_t irqn, IRQHandler_t handler)</div><div class="ttdoc">Register interrupt handler.</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e"><div class="ttname"><a href="group__irq__ctrl__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a></div><div class="ttdeci">@ SGI0_IRQn</div><div class="ttdoc">Software Generated Interrupt 0.</div><div class="ttdef"><b>Definition:</b> ref_irq_ctrl.txt:82</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_ga99e0f3f6945991d50e766b19e71e0222"><div class="ttname"><a href="group__irq__mode__defs.html#ga99e0f3f6945991d50e766b19e71e0222">IRQ_MODE_TRIG_EDGE_FALLING</a></div><div class="ttdeci">#define IRQ_MODE_TRIG_EDGE_FALLING</div><div class="ttdoc">Trigger: falling edge triggered interrupt.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gaa9a8e0968a4ccd57eb7544a16d05f24d"><div class="ttname"><a href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a></div><div class="ttdeci">#define IRQ_MODE_TRIG_EDGE</div><div class="ttdoc">Trigger: edge triggered interrupt.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gab0d022bbd15beb1a6578b5535d95f9cf"><div class="ttname"><a href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a></div><div class="ttdeci">#define IRQ_MODE_TYPE_IRQ</div><div class="ttdoc">Type: interrupt source triggers CPU IRQ line.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gacb276aa0488a9bf1aa56e1072d2a15a5"><div class="ttname"><a href="group__irq__mode__defs.html#gacb276aa0488a9bf1aa56e1072d2a15a5">IRQ_MODE_CPU_0</a></div><div class="ttdeci">#define IRQ_MODE_CPU_0</div><div class="ttdoc">CPU: interrupt targets CPU 0.</div></div>
<div class="ttc" id="airq__ctrl_8h_html_ac62964c04a7fed2c84aeea9e34f415e2"><div class="ttname"><a href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a></div><div class="ttdeci">int32_t IRQn_ID_t</div><div class="ttdoc">Interrupt ID number data type.</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:43</div></div>
</div><!-- fragment --> <h2 class="groupheader">Enumeration Type Documentation</h2>
<a id="ga7e1129cd8a196f4284d41db3e82ad5c8" name="ga7e1129cd8a196f4284d41db3e82ad5c8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7e1129cd8a196f4284d41db3e82ad5c8">&#9670;&#160;</a></span>IRQn_Type</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Definition of IRQn numbers. </p>
<p>The core exception enumeration names for IRQn values are defined in the <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a>.</p>
<p>The table below describes the core exception names in Cortex-A core. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e" name="gga7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e"></a>SGI0_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 0. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b" name="gga7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b"></a>SGI1_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 1. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07" name="gga7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07"></a>SGI2_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 2. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a310ac1f78af36e0e3b9f6b4f15bd9b68" name="gga7e1129cd8a196f4284d41db3e82ad5c8a310ac1f78af36e0e3b9f6b4f15bd9b68"></a>SGI3_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 3. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ac5c03a99c620ff116bafa4cf03dd9a07" name="gga7e1129cd8a196f4284d41db3e82ad5c8ac5c03a99c620ff116bafa4cf03dd9a07"></a>SGI4_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 4. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8adb8d49885011a278ed3c671904da7e6e" name="gga7e1129cd8a196f4284d41db3e82ad5c8adb8d49885011a278ed3c671904da7e6e"></a>SGI5_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 5. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a5f9b1989d051c60ad69147e644853a44" name="gga7e1129cd8a196f4284d41db3e82ad5c8a5f9b1989d051c60ad69147e644853a44"></a>SGI6_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 6. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8aa1bcd760176e11cdece4386818022631" name="gga7e1129cd8a196f4284d41db3e82ad5c8aa1bcd760176e11cdece4386818022631"></a>SGI7_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 7. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8aabbb7ca9433c474bfeade468e8c66455" name="gga7e1129cd8a196f4284d41db3e82ad5c8aabbb7ca9433c474bfeade468e8c66455"></a>SGI8_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 8. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8afa5f21d9fd3df5817a0f871b72bde681" name="gga7e1129cd8a196f4284d41db3e82ad5c8afa5f21d9fd3df5817a0f871b72bde681"></a>SGI9_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 9. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a12993bed484c7a70e6281b102d0e27e9" name="gga7e1129cd8a196f4284d41db3e82ad5c8a12993bed484c7a70e6281b102d0e27e9"></a>SGI10_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 10. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a7826ded51cd379774bb076819ff93cdb" name="gga7e1129cd8a196f4284d41db3e82ad5c8a7826ded51cd379774bb076819ff93cdb"></a>SGI11_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 11. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a3425bbf0a6da4d0398e63b48a1345d37" name="gga7e1129cd8a196f4284d41db3e82ad5c8a3425bbf0a6da4d0398e63b48a1345d37"></a>SGI12_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 12. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ace710506c7be1b3b7f9d4a1db2f75391" name="gga7e1129cd8a196f4284d41db3e82ad5c8ace710506c7be1b3b7f9d4a1db2f75391"></a>SGI13_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 13. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ae57c57a817378102db7bc66351c912f1" name="gga7e1129cd8a196f4284d41db3e82ad5c8ae57c57a817378102db7bc66351c912f1"></a>SGI14_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 14. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321" name="gga7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321"></a>SGI15_IRQn&#160;</td><td class="fielddoc"><p>Software Generated Interrupt 15. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a1d0271c3b3a369c16a9c05ab4ea72ca5" name="gga7e1129cd8a196f4284d41db3e82ad5c8a1d0271c3b3a369c16a9c05ab4ea72ca5"></a>VirtualMaintenanceInterrupt_IRQn&#160;</td><td class="fielddoc"><p>Virtual Maintenance Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8acc86d3c23264d2038fd8de56b65059f6" name="gga7e1129cd8a196f4284d41db3e82ad5c8acc86d3c23264d2038fd8de56b65059f6"></a>HypervisorTimer_IRQn&#160;</td><td class="fielddoc"><p>Hypervisor Timer Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a2dde3bb4fc49f71c15bba2c4f0cda2cd" name="gga7e1129cd8a196f4284d41db3e82ad5c8a2dde3bb4fc49f71c15bba2c4f0cda2cd"></a>VirtualTimer_IRQn&#160;</td><td class="fielddoc"><p>Virtual Timer Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8ac286832ada11ea1575a98149404d8aa7" name="gga7e1129cd8a196f4284d41db3e82ad5c8ac286832ada11ea1575a98149404d8aa7"></a>Legacy_nFIQ_IRQn&#160;</td><td class="fielddoc"><p>Legacy nFIQ Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a82e7e80a1d7d70bbe65b380bcda3f309" name="gga7e1129cd8a196f4284d41db3e82ad5c8a82e7e80a1d7d70bbe65b380bcda3f309"></a>SecurePhyTimer_IRQn&#160;</td><td class="fielddoc"><p>Secure Physical Timer Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8aff0bcb9be41e2ba389f9bf1d5f403145" name="gga7e1129cd8a196f4284d41db3e82ad5c8aff0bcb9be41e2ba389f9bf1d5f403145"></a>NonSecurePhyTimer_IRQn&#160;</td><td class="fielddoc"><p>Non-Secure Physical Timer Interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga7e1129cd8a196f4284d41db3e82ad5c8a1718b510599bbe8ebe34aee5c5aa3214" name="gga7e1129cd8a196f4284d41db3e82ad5c8a1718b510599bbe8ebe34aee5c5aa3214"></a>Legacy_nIRQ_IRQn&#160;</td><td class="fielddoc"><p>Legacy nIRQ Interrupt. </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a id="gaad6b03f73b3d3ea2ccbb122484e8bd36" name="gaad6b03f73b3d3ea2ccbb122484e8bd36"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaad6b03f73b3d3ea2ccbb122484e8bd36">&#9670;&#160;</a></span>IRQ_ClearPending()</h2>

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      <table class="memname">
        <tr>
          <td class="memname">int32_t IRQ_ClearPending </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Clear interrupt pending flag. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function clears the pending status of the interrupt identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 16) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga5ad17ad70f23d1ff36015ffac33d383d"><div class="ttname"><a href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Clears the given interrupt from being pending using GIC's ICPENDR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1614</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga7e1129cd8a196f4284d41db3e82ad5c8"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></div><div class="ttdeci">IRQn_Type</div><div class="ttdoc">Definition of IRQn numbers.</div><div class="ttdef"><b>Definition:</b> ref_irq_ctrl.txt:79</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga544cf4ae0159cc17e259d55898528248">&#9670;&#160;</a></span>IRQ_Disable()</h2>

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          <td class="memname">int32_t IRQ_Disable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Disable interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function disables forwarding of the corresponding interrupt to the CPU.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga2102399d255690c0674209a6faeec13d"><div class="ttname"><a href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Disables the given interrupt using GIC's ICENABLER register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1568</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4ad780a3dc23a1b6222de8adcd7c20a7">&#9670;&#160;</a></span>IRQ_Enable()</h2>

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          <td class="memname">int32_t IRQ_Enable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function enables forwarding of the corresponding interrupt to the CPU.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_gaeba215d9c4ec3599e0a168800288c3f3"><div class="ttname"><a href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Enables the given interrupt using GIC's ISENABLER register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1551</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga55638c35efdc7a197b51165929ef0c10">&#9670;&#160;</a></span>IRQ_EndOfInterrupt()</h2>

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          <td class="memname">int32_t IRQ_EndOfInterrupt </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Signal end of interrupt processing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function informs the interrupt controller that the interrupt service routine processing of the currently active interrupt request is completed.</p>
<p>The parameter irqn should specify the value previously returned by the <a class="el" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> or <a class="el" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> functions.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10">IRQ_EndOfInterrupt</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> (irqn == 0) {</div>
<div class="line">      IRQ_ID0 = 0U;</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_gac23f090f572a058b4a737f6613ded9cd"><div class="ttname"><a href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a></div><div class="ttdeci">__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)</div><div class="ttdoc">Writes the given interrupt number to the CPU's EOIR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1543</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga55638c35efdc7a197b51165929ef0c10"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10">IRQ_EndOfInterrupt</a></div><div class="ttdeci">int32_t IRQ_EndOfInterrupt(IRQn_ID_t irqn)</div><div class="ttdoc">Signal end of interrupt processing.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1376a5cf6ff38344a9bbbae080af5a0f">&#9670;&#160;</a></span>IRQ_GetActiveFIQ()</h2>

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          <td class="memname"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> IRQ_GetActiveFIQ </td>
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<p>Get ID number of current fast interrupt request (FIQ). </p>
<dl class="section return"><dt>Returns</dt><dd>interrupt ID number.</dd></dl>
<p>This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> <a class="code hl_function" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> (<span class="keywordtype">void</span>) {</div>
<div class="line">  <span class="comment">// FIQ is not supported, return invalid ID</span></div>
<div class="line">  <span class="keywordflow">return</span> ((<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)-1);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga1376a5cf6ff38344a9bbbae080af5a0f"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a></div><div class="ttdeci">IRQn_ID_t IRQ_GetActiveFIQ(void)</div><div class="ttdoc">Get ID number of current fast interrupt request (FIQ).</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1664e9fc682c3ace4b721906d6ce2b3d">&#9670;&#160;</a></span>IRQ_GetActiveIRQ()</h2>

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          <td class="memname"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> IRQ_GetActiveIRQ </td>
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<p>Get ID number of current interrupt request (IRQ). </p>
<dl class="section return"><dt>Returns</dt><dd>interrupt ID number.</dd></dl>
<p>This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> <a class="code hl_function" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> (<span class="keywordtype">void</span>) {</div>
<div class="line">  <a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn;</div>
<div class="line"> </div>
<div class="line">  irqn = (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code hl_function" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>();</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (irqn);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_gafc08bbc58b25fef0d24003313fd16eb8"><div class="ttname"><a href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a></div><div class="ttdeci">__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)</div><div class="ttdoc">Read the CPU's IAR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1535</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga1664e9fc682c3ace4b721906d6ce2b3d"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a></div><div class="ttdeci">IRQn_ID_t IRQ_GetActiveIRQ(void)</div><div class="ttdoc">Get ID number of current interrupt request (IRQ).</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8913613a9075a35410af0eb7b275d9e2">&#9670;&#160;</a></span>IRQ_GetEnableState()</h2>

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          <td class="memname">uint32_t IRQ_GetEnableState </td>
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          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
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<p>Get interrupt enable state. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is disabled, 1 - interrupt is enabled.</dd></dl>
<p>This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.</p>
<p>Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2">IRQ_GetEnableState</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  uint32_t enable;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    enable = <a class="code hl_function" href="core__ca_8h.html#abcd7d576ea634b1a708db9fda95d09df">GIC_GetEnableIRQ</a>((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    enable = 0U;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (enable);</div>
<div class="line">}</div>
<div class="ttc" id="acore__ca_8h_html_abcd7d576ea634b1a708db9fda95d09df"><div class="ttname"><a href="core__ca_8h.html#abcd7d576ea634b1a708db9fda95d09df">GIC_GetEnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get interrupt enable status using GIC's ISENABLER register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1560</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga8913613a9075a35410af0eb7b275d9e2"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2">IRQ_GetEnableState</a></div><div class="ttdeci">uint32_t IRQ_GetEnableState(IRQn_ID_t irqn)</div><div class="ttdoc">Get interrupt enable state.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa2a2df8fbc7bad465ada49bd690f65d5">&#9670;&#160;</a></span>IRQ_GetHandler()</h2>

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          <td class="memname"><a class="el" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a> IRQ_GetHandler </td>
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          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
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<p>Get the registered interrupt handler. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>registered interrupt handler function address.</dd></dl>
<p>This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code hl_typedef" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a> <a class="code hl_function" href="group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5">IRQ_GetHandler</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  IRQHandler h;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    h = IRQTable[irqn];</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    h = (<a class="code hl_typedef" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a>)0;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (h);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gaa2a2df8fbc7bad465ada49bd690f65d5"><div class="ttname"><a href="group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5">IRQ_GetHandler</a></div><div class="ttdeci">IRQHandler_t IRQ_GetHandler(IRQn_ID_t irqn)</div><div class="ttdoc">Get the registered interrupt handler.</div></div>
<div class="ttc" id="airq__ctrl_8h_html_a27589275c894aa295615df4764404b98"><div class="ttname"><a href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a></div><div class="ttdeci">void(* IRQHandler_t)(void)</div><div class="ttdoc">Interrupt handler data type.</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:37</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gadba142ee49ae8f52f76b603c926ad711">&#9670;&#160;</a></span>IRQ_GetMode()</h2>

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<p>Get interrupt mode configuration. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.</dd></dl>
<p>This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter. <a class="el" href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a> is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  uint32_t mode;</div>
<div class="line">  uint32_t val;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    mode = <a class="code hl_define" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a>;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Get trigger mode</span></div>
<div class="line">    val = <a class="code hl_function" href="core__ca_8h.html#a43cfac7327b49e2a89d63abc99b6b06a">GIC_GetConfiguration</a>((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> ((val &amp; 2U) != 0U) {</div>
<div class="line">      <span class="comment">// Corresponding interrupt is edge triggered</span></div>
<div class="line">      mode |= <a class="code hl_define" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a>;</div>
<div class="line">    } <span class="keywordflow">else</span> {</div>
<div class="line">      <span class="comment">// Corresponding interrupt is level triggered</span></div>
<div class="line">      mode |= <a class="code hl_define" href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a>;</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Get interrupt CPU targets</span></div>
<div class="line">    mode |= <a class="code hl_function" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn) &lt;&lt; <a class="code hl_define" href="irq__ctrl_8h.html#ab7527409c193021e65aaf4d519caea46">IRQ_MODE_CPU_Pos</a>;</div>
<div class="line"> </div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    mode = <a class="code hl_define" href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a>;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (mode);</div>
<div class="line">}</div>
<div class="ttc" id="acore__ca_8h_html_a43cfac7327b49e2a89d63abc99b6b06a"><div class="ttname"><a href="core__ca_8h.html#a43cfac7327b49e2a89d63abc99b6b06a">GIC_GetConfiguration</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)</div><div class="ttdoc">Get the interrupt configuration from the GIC's ICFGR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1646</div></div>
<div class="ttc" id="agroup__GIC__functions_html_gafccf881f9517592f30489bcabcb738a8"><div class="ttname"><a href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)</div><div class="ttdoc">Read the GIC's ITARGETSR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1513</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gadba142ee49ae8f52f76b603c926ad711"><div class="ttname"><a href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a></div><div class="ttdeci">uint32_t IRQ_GetMode(IRQn_ID_t irqn)</div><div class="ttdoc">Get interrupt mode configuration.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gaacb93ae158e548c54698a7230647804a"><div class="ttname"><a href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a></div><div class="ttdeci">#define IRQ_MODE_ERROR</div><div class="ttdoc">Bit indicating mode value error.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gabc31ba71612436a6ccc49342f35fec58"><div class="ttname"><a href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a></div><div class="ttdeci">#define IRQ_MODE_TRIG_LEVEL</div><div class="ttdoc">Trigger: level triggered interrupt.</div></div>
<div class="ttc" id="airq__ctrl_8h_html_ab7527409c193021e65aaf4d519caea46"><div class="ttname"><a href="irq__ctrl_8h.html#ab7527409c193021e65aaf4d519caea46">IRQ_MODE_CPU_Pos</a></div><div class="ttdeci">#define IRQ_MODE_CPU_Pos</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:67</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa399f9169f136b3930f0d50247aa22fc">&#9670;&#160;</a></span>IRQ_GetPending()</h2>

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<p>Get interrupt pending flag. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not pending, 1 - interrupt is pending.</dd></dl>
<p>This function retrieves the pending status of the interrupt identified by the irqn parameter.</p>
<p>Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc">IRQ_GetPending</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  uint32_t pending;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 16) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    pending = <a class="code hl_function" href="core__ca_8h.html#ab726a01df6ee9a480cc73910a06ddfb7">GIC_GetPendingIRQ</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    pending = 0U;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (pending &amp; 1U);</div>
<div class="line">}</div>
<div class="ttc" id="acore__ca_8h_html_ab726a01df6ee9a480cc73910a06ddfb7"><div class="ttname"><a href="core__ca_8h.html#ab726a01df6ee9a480cc73910a06ddfb7">GIC_GetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get interrupt pending status from GIC's ISPENDR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1577</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gaa399f9169f136b3930f0d50247aa22fc"><div class="ttname"><a href="group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc">IRQ_GetPending</a></div><div class="ttdeci">uint32_t IRQ_GetPending(IRQn_ID_t irqn)</div><div class="ttdoc">Get interrupt pending flag.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0a6a18c8fa2bc3183598439b56c507c3">&#9670;&#160;</a></span>IRQ_GetPriority()</h2>

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          <td class="memname">uint32_t IRQ_GetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
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<p>Get interrupt priority. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the priority of the interrupt identified by the irqn parameter.</p>
<p>The valid priority value can be from zero (0) to the value of <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a>. <a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> bit is set in returned value for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3">IRQ_GetPriority</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  uint32_t priority;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    priority = <a class="code hl_function" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    priority = <a class="code hl_define" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a>;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (priority);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga397048004654f792649742f95bf8ae67"><div class="ttname"><a href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Read the current interrupt priority from GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1664</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga0a6a18c8fa2bc3183598439b56c507c3"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3">IRQ_GetPriority</a></div><div class="ttdeci">uint32_t IRQ_GetPriority(IRQn_ID_t irqn)</div><div class="ttdoc">Get interrupt priority.</div></div>
<div class="ttc" id="agroup__irq__priority__defs_html_ga47b19866dc05c58c6923c313b371f881"><div class="ttname"><a href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a></div><div class="ttdeci">#define IRQ_PRIORITY_ERROR</div><div class="ttdoc">Bit indicating priority value error.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga061da812739bdba1e32765ed6501b83c">&#9670;&#160;</a></span>IRQ_GetPriorityGroupBits()</h2>

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          <td class="memname">uint32_t IRQ_GetPriorityGroupBits </td>
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          <td class="paramname"></td><td>)</td>
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<p>Get priority grouping field split point. </p>
<dl class="section return"><dt>Returns</dt><dd>current number of MSB bits included in the group priority field comparison with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.</p>
<p><a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> value is returned when priority grouping is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> (<span class="keywordtype">void</span>) {</div>
<div class="line">  uint32_t bp;</div>
<div class="line"> </div>
<div class="line">  bp = <a class="code hl_function" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a>() &amp; 0x07U;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (7U - bp);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_gaa7046d8206ddd4696716726e68f85906"><div class="ttname"><a href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)</div><div class="ttdoc">Read the current group priority and subpriority split point from CPU's BPR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1696</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga77632ae73f1ba46c4a9a0c12e6bc4869">&#9670;&#160;</a></span>IRQ_GetPriorityMask()</h2>

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          <td class="memname">uint32_t IRQ_GetPriorityMask </td>
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<p>Get priority masking threshold. </p>
<dl class="section return"><dt>Returns</dt><dd>current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the priority masking threshold for the current processor.</p>
<p><a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> value is returned if priority masking is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869">IRQ_GetPriorityMask</a> (<span class="keywordtype">void</span>) {</div>
<div class="line">  <span class="keywordflow">return</span> <a class="code hl_function" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a>();</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga2c5f9e5637560fc9d5c29d772580a728"><div class="ttname"><a href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)</div><div class="ttdoc">Read the current interrupt priority mask from CPU's PMR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1680</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga77632ae73f1ba46c4a9a0c12e6bc4869"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869">IRQ_GetPriorityMask</a></div><div class="ttdeci">uint32_t IRQ_GetPriorityMask(void)</div><div class="ttdoc">Get priority masking threshold.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga03ea5d5d67a89acff8a5b02286795a99">&#9670;&#160;</a></span>IRQ_Initialize()</h2>

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          <td class="memname">int32_t IRQ_Initialize </td>
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          <td class="paramname"></td><td>)</td>
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<p>Initialize interrupt controller. </p>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function initializes interrupt controller.</p>
<p>It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"> </div>
<div class="line"><span class="preprocessor">#ifndef IRQ_GIC_LINE_COUNT</span></div>
<div class="line"><span class="preprocessor">#define IRQ_GIC_LINE_COUNT      (1020U)</span></div>
<div class="line"><span class="preprocessor">#endif</span></div>
<div class="line"> </div>
<div class="line"><span class="keyword">static</span> IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };</div>
<div class="line"> </div>
<div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a> (<span class="keywordtype">void</span>) {</div>
<div class="line">  uint32_t i;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">for</span> (i = 0U; i &lt; IRQ_GIC_LINE_COUNT; i++) {</div>
<div class="line">    IRQTable[i] = (IRQHandler)NULL;</div>
<div class="line">  }</div>
<div class="line">  <a class="code hl_function" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a>();</div>
<div class="line">  <span class="keywordflow">return</span> (0);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga818881f69aae3eef6eb996bee6f6c63e"><div class="ttname"><a href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a></div><div class="ttdeci">__STATIC_INLINE void GIC_Enable(void)</div><div class="ttdoc">Initialize and enable the GIC.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1845</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gac1fcc16fb8e488d315cfa496f1d71db3">&#9670;&#160;</a></span>IRQ_SetHandler()</h2>

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          <td class="memname">int32_t IRQ_SetHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a>&#160;</td>
          <td class="paramname"><em>handler</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Register interrupt handler. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">handler</td><td>interrupt handler function address </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, <a class="code hl_typedef" href="irq__ctrl_8h.html#a27589275c894aa295615df4764404b98">IRQHandler_t</a> handler) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    IRQTable[irqn] = handler;</div>
<div class="line">    status =  0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gab35da69354d2e515931580a1308a3a85">&#9670;&#160;</a></span>IRQ_SetMode()</h2>

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          <td class="memname">int32_t IRQ_SetMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>mode</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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<p>Configure interrupt request mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>mode configuration </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt (see <a class="el" href="group__irq__mode__defs.html">IRQ Mode Bit-Masks</a>) identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t mode) {</div>
<div class="line">  int32_t status;</div>
<div class="line">  uint32_t val;</div>
<div class="line">  uint8_t cfg;</div>
<div class="line">  uint8_t secure;</div>
<div class="line">  uint8_t cpu;</div>
<div class="line"> </div>
<div class="line">  status = 0;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <span class="comment">// Check triggering mode</span></div>
<div class="line">    val = (mode &amp; <a class="code hl_define" href="irq__ctrl_8h.html#a2fafbaf2f6da5241ad97af6c493fa218">IRQ_MODE_TRIG_Msk</a>);</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> (val == <a class="code hl_define" href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a>) {</div>
<div class="line">      cfg = 0x00U;</div>
<div class="line">    } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (val == <a class="code hl_define" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a>) {</div>
<div class="line">      cfg = 0x02U;</div>
<div class="line">    } <span class="keywordflow">else</span> {</div>
<div class="line">      status = -1;</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Check interrupt type</span></div>
<div class="line">    val = mode &amp; <a class="code hl_define" href="irq__ctrl_8h.html#a7b0581db3736a143cd582cd2457bf3cc">IRQ_MODE_TYPE_Msk</a>;</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> (val != <a class="code hl_define" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a>) {</div>
<div class="line">      status = -1;</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Check interrupt domain</span></div>
<div class="line">    val = mode &amp; <a class="code hl_define" href="irq__ctrl_8h.html#afdc87f9fda2bafac2b0399ebdb39bf3e">IRQ_MODE_DOMAIN_Msk</a>;</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> (val == <a class="code hl_define" href="group__irq__mode__defs.html#ga7498851a6a7f3e2c5e087041617f5be7">IRQ_MODE_DOMAIN_NONSECURE</a>) {</div>
<div class="line">      secure = 0;</div>
<div class="line">    } <span class="keywordflow">else</span> {</div>
<div class="line">      <span class="comment">// Check security extensions support</span></div>
<div class="line">      val = <a class="code hl_function" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a>() &amp; (1UL &lt;&lt; 10U);</div>
<div class="line"> </div>
<div class="line">      <span class="keywordflow">if</span> (val != 0U) {</div>
<div class="line">        <span class="comment">// Security extensions are supported</span></div>
<div class="line">        secure = 1;</div>
<div class="line">      } <span class="keywordflow">else</span> {</div>
<div class="line">        status = -1;</div>
<div class="line">      }</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Check interrupt CPU targets</span></div>
<div class="line">    val = mode &amp; <a class="code hl_define" href="irq__ctrl_8h.html#a96f739279c27f3e56ede4f28de4a48d8">IRQ_MODE_CPU_Msk</a>;</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> (val == <a class="code hl_define" href="group__irq__mode__defs.html#gad3d0505689768247c67495b7359e147f">IRQ_MODE_CPU_ALL</a>) {</div>
<div class="line">      cpu = 0xFF;</div>
<div class="line">    } <span class="keywordflow">else</span> {</div>
<div class="line">      cpu = val &gt;&gt; <a class="code hl_define" href="irq__ctrl_8h.html#ab7527409c193021e65aaf4d519caea46">IRQ_MODE_CPU_Pos</a>;</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Apply configuration if no mode error</span></div>
<div class="line">    <span class="keywordflow">if</span> (status == 0) {</div>
<div class="line">      <a class="code hl_function" href="core__ca_8h.html#a5dffcd04b18d2c3ee5a410e185ce5108">GIC_SetConfiguration</a>((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, cfg);</div>
<div class="line">      <a class="code hl_function" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a>       ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, cpu);</div>
<div class="line"> </div>
<div class="line">      <span class="keywordflow">if</span> (secure != 0U) {</div>
<div class="line">        <a class="code hl_function" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, secure);</div>
<div class="line">      }</div>
<div class="line">    }</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="acore__ca_8h_html_a5dffcd04b18d2c3ee5a410e185ce5108"><div class="ttname"><a href="core__ca_8h.html#a5dffcd04b18d2c3ee5a410e185ce5108">GIC_SetConfiguration</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)</div><div class="ttdoc">Sets the interrupt configuration using GIC's ICFGR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1629</div></div>
<div class="ttc" id="acore__ca_8h_html_ab875d63dc51a75149802945bb00e2695"><div class="ttname"><a href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)</div><div class="ttdoc">Set the interrupt group from the GIC's IGROUPR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1745</div></div>
<div class="ttc" id="agroup__GIC__functions_html_ga7d93d39736ef5e379e6511430ee6e75f"><div class="ttname"><a href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_DistributorInfo(void)</div><div class="ttdoc">Read the GIC's TYPER register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1486</div></div>
<div class="ttc" id="agroup__GIC__functions_html_gae86bba705d0d4ef812b84d29d7b3ca2b"><div class="ttname"><a href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)</div><div class="ttdoc">Sets the GIC's ITARGETSR register for the given interrupt.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1503</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_ga7498851a6a7f3e2c5e087041617f5be7"><div class="ttname"><a href="group__irq__mode__defs.html#ga7498851a6a7f3e2c5e087041617f5be7">IRQ_MODE_DOMAIN_NONSECURE</a></div><div class="ttdeci">#define IRQ_MODE_DOMAIN_NONSECURE</div><div class="ttdoc">Domain: interrupt is targeting non-secure domain.</div></div>
<div class="ttc" id="agroup__irq__mode__defs_html_gad3d0505689768247c67495b7359e147f"><div class="ttname"><a href="group__irq__mode__defs.html#gad3d0505689768247c67495b7359e147f">IRQ_MODE_CPU_ALL</a></div><div class="ttdeci">#define IRQ_MODE_CPU_ALL</div><div class="ttdoc">CPU: interrupt targets all CPUs.</div></div>
<div class="ttc" id="airq__ctrl_8h_html_a2fafbaf2f6da5241ad97af6c493fa218"><div class="ttname"><a href="irq__ctrl_8h.html#a2fafbaf2f6da5241ad97af6c493fa218">IRQ_MODE_TRIG_Msk</a></div><div class="ttdeci">#define IRQ_MODE_TRIG_Msk</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:48</div></div>
<div class="ttc" id="airq__ctrl_8h_html_a7b0581db3736a143cd582cd2457bf3cc"><div class="ttname"><a href="irq__ctrl_8h.html#a7b0581db3736a143cd582cd2457bf3cc">IRQ_MODE_TYPE_Msk</a></div><div class="ttdeci">#define IRQ_MODE_TYPE_Msk</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:58</div></div>
<div class="ttc" id="airq__ctrl_8h_html_a96f739279c27f3e56ede4f28de4a48d8"><div class="ttname"><a href="irq__ctrl_8h.html#a96f739279c27f3e56ede4f28de4a48d8">IRQ_MODE_CPU_Msk</a></div><div class="ttdeci">#define IRQ_MODE_CPU_Msk</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:68</div></div>
<div class="ttc" id="airq__ctrl_8h_html_afdc87f9fda2bafac2b0399ebdb39bf3e"><div class="ttname"><a href="irq__ctrl_8h.html#afdc87f9fda2bafac2b0399ebdb39bf3e">IRQ_MODE_DOMAIN_Msk</a></div><div class="ttdeci">#define IRQ_MODE_DOMAIN_Msk</div><div class="ttdef"><b>Definition:</b> irq_ctrl.h:63</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga88aedf1dee1061783e6c05c535e7b6c4">&#9670;&#160;</a></span>IRQ_SetPending()</h2>

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          <td class="memname">int32_t IRQ_SetPending </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set interrupt pending flag. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the pending status of the interrupt identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga18fbddf7f3594df141c97f61a71da47c"><div class="ttname"><a href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Sets the given interrupt as pending using GIC's ISPENDR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1600</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa90aed20ac94420fff4bbbf55c12d4c2">&#9670;&#160;</a></span>IRQ_SetPriority()</h2>

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          <td class="memname">int32_t IRQ_SetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>&#160;</td>
          <td class="paramname"><em>irqn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set interrupt priority value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>interrupt priority value </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the priority of the interrupt identified by the irqn parameter.</p>
<p>Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value depends on the number of implemented priority levels.</p>
<p>The number of implemented priority bits can be determined by setting value <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a> to arbitrary irqn and by retrieving the actual stored value with IRQ_GetPriority function.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> (<a class="code hl_typedef" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t priority) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> ((irqn &gt;= 0) &amp;&amp; (irqn &lt; IRQ_GIC_LINE_COUNT)) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> ((<a class="code hl_enumeration" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, priority);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga27b9862b58290276851ec669cabf0f71"><div class="ttname"><a href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set the priority for the given interrupt in the GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1655</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gabaa4074988ea9e30523f7ed5a86953c2">&#9670;&#160;</a></span>IRQ_SetPriorityGroupBits()</h2>

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          <td class="memname">int32_t IRQ_SetPriorityGroupBits </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>bits</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set priority grouping field split point. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">bits</td><td>number of MSB bits included in the group priority field comparison </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.</p>
<p>The number of implemented group priority bits can be determined by setting value <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a> and by retrieving the actual stored value with <a class="el" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> function. Function returns error status -1 if priority grouping is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code hl_function" href="group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2">IRQ_SetPriorityGroupBits</a> (uint32_t bits) {</div>
<div class="line">  int32_t status;</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> (bits == <a class="code hl_define" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a>) {</div>
<div class="line">    bits = 7U;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">if</span> (bits &lt; 8U) {</div>
<div class="line">    <a class="code hl_function" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (7U - bits);</div>
<div class="line">    status = 0;</div>
<div class="line">  } <span class="keywordflow">else</span> {</div>
<div class="line">    status = -1;</div>
<div class="line">  }</div>
<div class="line"> </div>
<div class="line">  <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_ga5dfedeb5403656a77e0fef4e1cc2c0c6"><div class="ttname"><a href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)</div><div class="ttdoc">Configures the group priority and subpriority split point using CPU's BPR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1688</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_gabaa4074988ea9e30523f7ed5a86953c2"><div class="ttname"><a href="group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2">IRQ_SetPriorityGroupBits</a></div><div class="ttdeci">int32_t IRQ_SetPriorityGroupBits(uint32_t bits)</div><div class="ttdoc">Set priority grouping field split point.</div></div>
<div class="ttc" id="agroup__irq__priority__defs_html_gabaa4e91ab84dbe5f669080af6d0d81fa"><div class="ttname"><a href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a></div><div class="ttdeci">#define IRQ_PRIORITY_Msk</div><div class="ttdoc">Interrupt priority value bit-mask.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3a79888f72bd1db45f0b9a59dbaa2337">&#9670;&#160;</a></span>IRQ_SetPriorityMask()</h2>

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          <td class="memname">int32_t IRQ_SetPriorityMask </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set priority masking threshold. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>priority masking threshold value </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the priority masking threshold for the current processor.</p>
<p>It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor. Function returns error status -1 if priority masking is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code hl_function" href="group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337">IRQ_SetPriorityMask</a> (uint32_t priority) {</div>
<div class="line">  <a class="code hl_function" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (priority);</div>
<div class="line">  <span class="keywordflow">return</span> (0);</div>
<div class="line">}</div>
<div class="ttc" id="agroup__GIC__functions_html_gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><div class="ttname"><a href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)</div><div class="ttdoc">Set the interrupt priority mask using CPU's PMR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1672</div></div>
<div class="ttc" id="agroup__irq__ctrl__gr_html_ga3a79888f72bd1db45f0b9a59dbaa2337"><div class="ttname"><a href="group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337">IRQ_SetPriorityMask</a></div><div class="ttdeci">int32_t IRQ_SetPriorityMask(uint32_t priority)</div><div class="ttdoc">Set priority masking threshold.</div></div>
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